1. Field of the Invention
The present invention relates to an exposure processing system, an exposure processing method and a method for manufacturing a semiconductor device for forming a fine pattern.
2. Description of the Related Art
The performance of the semiconductor device is greatly dependent on the dimensional accuracy of a fine pattern. One of the most important problems relating to the dimensional accuracy is how to decrease dimensional dispersion in a wafer plane. The dimensional dispersion in the wafer plane is considered to include a dimensional dispersion caused by the exposure apparatus, a dimensional dispersion caused by the coating-developing apparatus, and a dimensional dispersion caused by the mask process.
The dimensional dispersion in the wafer plane is also generated among a plurality of wafers in the same lot. The dimensional dispersion of this type is derived mainly from the exposure processing system. The exposure processing system comprises a coating-developing apparatus and an exposure apparatus.
The coating-developing apparatus comprises a hot plate apparatus including a plurality of hot plate apparatus units for PEB (Post Exposure Bake). The coating-developing apparatus further comprises a developing apparatus including a plurality of developing apparatus units. The plurality of hot plate apparatus units has individual differences. Likewise, the plurality of developing apparatus units have individual differences. Therefore that, even if the PEB treatment and the development are carried out under the same conditions, the dimensional dispersion in the wafer plane tend to be different depending on the hot plate apparatus unit and the developing apparatus unit that to be used.
It is possible to control the dimensional dispersion in the wafer plane by controlling the controllable parameter (e.g. temperature) of the hot plate apparatus and the controllable parameter (e.g. heating time) of the developing apparatus.
However, it is very difficult to control the parameters referred to above in respect of all the combinations of the hot plate apparatus units and the developing apparatus units in a manner to suppress the dimensional dispersion in the wafer plane. Further, any publication has not yet been found in respect of the technology for suppressing the dimensional dispersion in the wafer plane in conjunction with all the combinations of the hot plate apparatus units and the developing apparatus units.